The present invention relates to an input circuit for use preferably in a CMOS semiconductor memory.
An input buffer for a semiconductor memory should be able to receive a TTL input signal (being in the range of 0.8 to 2.0 volts) and generate an output signal in a voltage range corresponding to the chip (generally between VSS and VCC), which in the case of CMOS memories today is 0 volts to 5 volts. Another requirement is that the input buffer must be able to drive high internal chip capacitances.
The problem which is solved by the present invention will be understood from consideration of the conventional input buffer circuit illustrated in FIG. 1 and its shortcomings. The problem with the circuit of FIG. 1 concerns the compromise made between speed of operation and standby current. As will be explained, these have been mutually inconsistent goals, i.e. to achieve increased speed, one sacrifices standby current. The present invention overcomes this problem.
FIG. 1 shows a conventional CMOS input buffer circuit 10 formed of field effect transistors (FETs) which are all enhancement mode devices. Circuit 10 receives an input at 12 and applies it to a first inverter stage 14 comprising a CMOS pair of transistors 16, 18. Device 16 is a p-channel device, whereas device 18 is an n-channel device. The source-drain paths of transistors 16, 18 are connected in series between VCC and ground, as illustrated. Input 12 is coupled to the gate electrodes of each of these transistors. A node A between the source of transistors 16 and the drain of transistor 18 provides an input to the second stage inverter 20. Inverter 20 comprises another pair of CMOS transistors including transistors 24 and 26 connected in a fashion identical to stage 14. The output node B of stage 22 is provided to the capacitive load of the chip as represented by capacitor 28.
In FIG. 1, if the input voltage is 2.0 volts, then transistors 16 and 18 will both be turned on. Current will flow from VCC to ground through the source-drain paths of these transistors. Transistor 18 will be sized approximately four or five times larger than transistor 16 in order to insure that the voltage at node A is at or near ground when the input voltage is at a TTL logic "1" level of about 2.0 volts. In actuality, the voltage at node A may be about 1.0 volts at this condition, and as a result, some current will flow in the second stage 20. The output of inverter stage 20 will have the same logic value as input 12.
Consider that the capacity of the load is about 5 picofarads (pf). To drive this capacity, the transistors in output stage 20 will need a channel width typically of about 200 microns, using a guideline of about 40 microns per pf for an n-channel transistor. This is a fairly large transistor, and the transistors in the first stage 14 must be large because node A must drive each of transistors 24 and 26. The current through the first stage will be significant. To reduce this standby current, more inverter stages could be added. This would allow downsizing the transistors in the first stage. However, adding stages will increase the delay in the transitions in the input and the output. This undesirable result is overcome by the present invention.